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82562G 10/100 mbps platform lan connect (plc) networking silicon datasheet product features 1 this device is lead-free. that is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. the material declaration data sheet, which includes lead impurity levels and the concentration of other restriction on hazardous substances (rohs)- banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_ic_package.pdf#pagemode=bookmarks in addition, this device has been tested and conf orms to the same parametric specifications as previous versions of the device. for more information regarding lead-free product s from intel corporation, contact your intel field sales representative. additional features the 82562G plc supports drop-in replacement with the 82562et. if it is not used as a drop- in replacement, strapping options enable new operating modes: ? led support for three logic configurations. ? lan disable function using one pin. ? increased transmit strength. the receive ber performance increases the margin for cable length. return loss performance is improved. ieee 802.3 10base-t/100base-tx compliant physical layer interface ieee 802.3u auto-negotiation support digital adaptive equalization control link status interrupt capability xor tree mode support 3-port led support (speed, link and activity) 10base-t auto-polarity correction lan connect interface diagnostic loopback mode 1:1 transmit transformer ratio support low power (less than 300 mw in active transmit mode) reduced power in ?unplugged mode? (less than 50 mw) automatic detection of ?unplugged mode? 3.3 v device lead-free 1 48-pin shrink small outline package for both leaded and lead-free designs. (devices that are lead-free are marked with a circled ?e3? and have the product code prefix: luxxxxxx). revision 1.3 april 2005
datasheet revision history revision revision date description 1.0 october 2004 initial release (confidential status). 1.1 november 2004 ? updated lead-free device information. ? updated table 1 and table 2 to reflect correct hardware configurations and led logic functionality. ? corrected signal names to match design guide and reference schemat- ics. 1.2 january 2005 ? added a note for phy signals rbias100 and rbias10 to section 4.3. 1.3 april 2005 ? added internal/external pull-up/pull-down resistor values to the hardware configuration table and signal definition tables for testen, isol_exec, isol_ti, isol_tck, and adv10/lan_disable# information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or oth erwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such p roducts, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel? products inclu ding liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual p roperty right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 82562G plc may contain design defects or errors known as errata which may cause the product to deviate from published speci fications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel' s website at http://www.intel.com. copyright ? 2005, intel corporation * other brands and names are the property of their respective owners.
datasheet i 82562G ? networking silicon contents 1.0 introduction................................................................................................................ ......... 1 1.1 overview .................................................................................................................... .. 1 1.2 references.................................................................................................................. .1 1.3 product codes ............................................................................................................. 1 2.0 82562G architectural overview.......................................................................................... 3 2.1 lan connect interface.................................................................................................3 2.1.1 reset/synchronize operations ..............................................................................4 2.1.2 reset considerations ............................................................................................ 4 2.1.3 lan connect clock operations............................................................................. 5 2.2 hardware configuration ............................................................................................... 5 3.0 performance enhancements.............................................................................................. 7 3.1 new usage modes: 1, 2, 3, and 4................................................................................ 7 3.1.1 pin usage for modes 1, 2, 3, and 4 .......................................................................7 3.1.2 enhanced tx mode................................................................................................ 8 4.0 82562G signal descriptions............................................................................................... 9 4.1 signal type definitions ............................................................................................... 9 4.2 twisted pair ethernet (tpe) pins ............................................................................... 9 4.3 external bias pins ....................................................................................................... 9 4.4 clock pins ................................................................................................................. 10 4.5 platform lan connect interface pins .......................................................................10 4.6 led pins ................................................................................................................... 11 4.7 miscellaneous control pins .......................................................................................11 4.8 power and ground connections ...............................................................................12 5.0 physical layer interface functionality..............................................................................13 5.1 100base-tx mode....................................................................................................13 5.1.1 100base-tx transmit blocks.............................................................................13 5.1.2 100base-tx receive blocks..............................................................................15 5.2 10base-t mode ........................................................................................................16 5.2.1 10base-t transmit blocks .................................................................................16 5.2.2 10base-t receive blocks ..................................................................................16 5.3 analog references.....................................................................................................17 5.4 dynamic reduced power & auto plugging detection................................................17 5.4.1 auto plugging detection ......................................................................................18 5.4.2 dynamic reduced power ....................................................................................18 5.4.3 configuration .......................................................................................................18 6.0 platform lan connect registers .....................................................................................19 6.1 medium dependent interface (mdi) registers 0 through 7 .......................................19 6.1.1 register 0: control register bit definitions ........................................................19 6.1.2 register 1: status register bit definitions ..........................................................20 6.1.3 register 2: phy identifier register bit definitions ..............................................21 6.1.4 register 3: phy identifier register bit definitions ..............................................21 6.1.5 register 4: auto-negotiation advertisement register bit definitions .................21
ii datasheet 82562G ? networking silicon 6.1.6 register 5: auto-negotiation link partner ability register bit definitions .......... 22 6.1.7 register 6: auto-negotiation expansion register bit definitions ....................... 22 6.2 mdi registers 8 through 15 ....................................................................................... 23 6.3 mdi registers 16 through 31 ..................................................................................... 23 6.3.1 register 16: phy status and control register bit definitions ............................ 23 6.3.2 register 17: phy unit special control bit definitions ........................................ 24 6.3.3 register 18: reserved ........................................................................................ 24 6.3.4 register 19: 100base-tx receive false carrier counter bit definitions ......... 25 6.3.5 register 20: 100base-tx receive disconnect counter bit definitions ............ 25 6.3.6 register 21: 100base-tx receive erro r frame counter bit definitions ........... 25 6.3.7 register 22: receive symbol error counter bit definitions ............................... 25 6.3.8 register 23: 100base-tx receive premature end of frame error counter bit definitions ............................................................................... 25 6.3.9 register 24: 10base-t receive end of frame error counter bit definitions .... 26 6.3.10 register 25: 10base-t transmit jabber detect counter bit definitions ........... 26 6.3.11 register 27: phy unit special control bit definitions ........................................ 27 7.0 82562G test port functionality........................................................................................ 29 7.1 asynchronous test mode .......................................................................................... 29 7.2 test function description .......................................................................................... 29 8.0 electrical and timing specifications................................................................................. 31 8.1 absolute maximum ratings ....................................................................................... 31 8.2 dc characteristics .................................................................................................... 31 8.2.1 x1 clock dc specifications ................................................................................ 31 8.2.2 lan connect interface dc specifications .......................................................... 32 8.2.3 led dc specifications ....................................................................................... 32 8.2.4 10base-t voltage and current dc specifications ............................................ 32 8.2.5 100base-tx voltage and current dc specifications ........................................ 33 8.3 ac characteristics ..................................................................................................... 34 8.3.1 10base-t normal link pulse (nlp) timing parameters ................................... 34 8.3.2 auto-negotiation fast link pulse (flp) timing parameters .............................. 35 8.3.3 100base-tx transmitter ac specifications ...................................................... 36 8.3.4 reset (rstsync) ac specifications ................................................................ 36 9.0 package and pinout information ...................................................................................... 37 9.1 package information .................................................................................................. 37 9.2 pinout information ...................................................................................................... 38 9.2.1 82562G pin assignments ................................................................................... 38 9.2.2 82562G shrink small outline package diagram ................................................ 39
networking silicon ? 82562G datasheet 1 1.0 introduction this document is applicable to the intel ? 82562G 10/100 mbps platform lan connect device, a member of the 82562G fast ethernet device family. 1.1 overview the intel ? 82562G 10/100 mbps platform lan connect is a highly-integrated device designed for 10 or 100 mbps ethernet systems. it is based on the ieee 10base-t and 100base-tx standards. the ieee 802.3u standard for 100base-tx defines networking over two pairs of category 5 unshielded twisted pair cable or type 1 shielded twisted pair cable. the 82562G complies with the ieee 802.3u auto-n egotiation standard and the ieee 802.3x full duplex flow control standard. the 82562G also in cludes a phy interface compliant to the current platform lan connect interface. 1.2 references ? ieee 802.3 standard for local and metropolitan area networks, institute of electrical and electronics engineers. ? 82562et(em) and 82562Gt(g) lan on motherboard design guide. intel corporation. ? intel ? i/o controller hub 6 (ich6) family extern al design specification (eds), volume 1, revision 1.5v1. intel corporation. ? intel ? i/o controller hub 6 (ich6) family extern al design specification (eds), volume 2, revision 1.5v2. intel corporation. ? lan connect interface specification. intel corporation. ? i/o control hub 2, 3, and 4 eeprom map and programming information. intel corporation. ? i/o control hub 5, 6, and 7 eeprom map and programming information. intel corporation. programming information can be obtained through your local intel representatives. 1.3 product codes the product ordering code for the 82562G is: ep82562G. the product ordering code for the 82562G lead-free version is: lu82562G.
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networking silicon ? 82562G datasheet 3 2.0 82562G architectural overview the 82562G plc is a 3.3 v device in a 48-pin sh rink small outline package (ssop) that is designed to work only in data terminal equipment (dte) mode. in normal operating mode, the 82562G incorporates all active circuitr y required to interface with the intel ? ichx device with an integrated 10/100 mbps lan controller. the 82562G supports a direct interface to all media access control (mac) components that meet the platform lan connect interface specification. figure 1 shows a block diagram of the 82562G architecture. figure 1. 82562G plc block diagram 2.1 lan connect interface the 82562G supports a lan connect interface (lci) as specified in the lci specification. the lan connect is the i/o control hub 2 (ich2) in terface to the 82562G. the lci uses an 8-pin interface, which reduces the pin count from 15, fo r an media independent interface (mii) phy. in addition, its signaling protocol provides greater functionality, such as dynamic power reduction, from a plc in comparison to a standard mii phy. figure 2 shows how the 82562G can be used in a 10/100 mbps ichx design. equalizer & blw correction crs/link 10 detection digital clock recovery (100) digital clock recovery (10) digital equalizer adaptation 100base-tx pcs transmit dac 10/100 clock generator rdn/rdp tdn/tdp lan connect interface port led drivers liled# actled# spdled# auto- negotiation control registers 10base-t pcs mdi/mdi-x 3 3 jrstsync jtxd[2:0] jrxd[2:0] jclk bias & band- gap voltage circuit x2 x1 crystal 25 mhz
82562G ? networking silicon 4 datasheet figure 2. 82562G plc 10/100 mbps ethernet solution 2.1.1 reset/synchronize operations the reset/synchronize signal used by the lan connect interface is driven by the ichx integrated lan device. it has two functions: ? synchronize. when this pin is activated synchronously for only one lan connect clock, it is used for synchronization between the ichx integrated lan and phy on lan connect word boundaries. ? reset. when this pin is asserted beyond one l an connect clock, the 82562G uses this signal as a reset signal. to ensure a reset of the 82562G, the reset should remain active for at least 500 s. 2.1.2 reset considerations when the 82562G reset signal (jrstsync) is asserted for at least 500 s, all internal circuits are reset. the 82562G can also be reset by setting the mii register reset bit equal to 1 (register 0, bit 15). the 82562G filters out jrstsync pulses with a width of less than 200 ns to distinguish between a reset and synchronize pulse. again, the reset signal should be longer than 500 s to reset the 82562G. i/o control hub 4 (ich4) lan controller 82562ez (platform lan connect device) transmit differential pair (tdp/tdn) receive differential pair (rdp/rdn) system bus interface magnetics i/o control hub lan controller 82562G plc
networking silicon ? 82562G datasheet 5 2.1.3 lan connect clock operations the 82562G drives the platform lan connect clock (jclk) at one of two possible frequencies depending upon its operation speed. when the 82562G is in 100base-tx mode it drives jclk at 50 mhz. when the 82562G is in 10base-t mode it drives jclk at 5 mhz. the lan connect clock does not stop during normal operation under any conditions. in reduced power mode, the 82562G drives jclk at 5 mhz, which is required for proper filtering of incoming packets for applications such as wake on lan (wol). 2.2 hardware configuration four pins, test enable (testen), test clock (isol_tck), test input (isol_ti), and test execute (isol_exec), define the general operation of the 82562G. table 1 lists the pin settings for the different modes of operation. table 1. 82562G hardware configuration testen isol _tck isol _ti isol_ exec mode comments 0000 82562G family mode 0: ? leds are 82562e-compatible (?a? configuration) ? lan_disable# pin is used as adv10 (auto-negotiation advertise 10m only) alternative mode: drop-in replacement for existing 82562e- based designs the isol_tck, isol_tci, and isol_exec, and adv10/ lan_disable# pins have internal 10 k ? pull-down resistors and should not be connected for mode 0 (refer to table 2 ). for the alternative 82562e drop-in replacement mode, pins may optionally be used as a lan disable. 0011 82562G family mode 1: ? leds are in configuration b ? lan_disable# pin is single pin lan disable (tri-state and full power down function) the isol_tck pin has an internal 10 k ? pull-down resistor and should not be connected for mode 1 (refer to table 2 ). 0 1 1 1 isolate tri-state and power down. 1 0 1 0 testing mode 1 0 0 0 xor tree board testing plus tri-state. 1001 82562G family mode 2: same as 0011 except that leds are in configuration c the isol_tck and isol_ti pins have 10 k ? internal pull-down resistors and should not be connected for mode 2 (refer to table 2 ). 1011 82562G family mode 3: same as 0011 except enhance tx rise and fall times. the isol_tck pin has an internal 10 k ? pull-down resistor and should not be connected for mode 3. 1100 82562G family mode 4: same as 1001 except enhance tx rise and fall times. the isol_ti and isol_exec pins have internal 10 k ? pull- down resistors and should not be connected for mode 4.
82562G ? networking silicon 6 datasheet note: combinations not shown in table 1 are reserved and should not be used. 1101reserved the isol_ti pin has an internal 10 k ? pull-down resistor and should not be connected. 1 1 1 0 reserved testing the isol_exec pin has an internal 10 k ? pull-down resistor and should not be connected. 1 1 1 1 power-down mode tri-state and power down. table 1. 82562G hardware configuration testen isol _tck isol _ti isol_ exec mode comments table 2. led logic functionality mode/configuration actled# spdled# liled# configuration a: 82562et-compatible activity speed 100 mb asserted if valid link is present at 10 mb or 100 mb configuration b: intel gbe mode activity link and speed 100 mb asserted if valid link is present at 10 mb or 100 mb configuration c: alternative mode activity link and speed 100 mb link and speed 10 mb
networking silicon ? 82562G datasheet 7 3.0 performance enhancements 3.1 new usage modes: 1, 2, 3, and 4 82562G supports several new features that offer design flexibility and reduced bom cost compared to the 82562et plc device. to implem ent these new features, a board design must include the proper pull-up and/or pull-down strapping resistor options. refer to the 82562Gt/ 82562Gz/82562Gx/82562G lan on motherboard design guide for more information. table 3 lists the four new modes. 3.1.1 pin usage for modes 1, 2, 3, and 4 to use modes 1, 2, 3, or 4, the following pins need to be reviewed (refer to table 1 ): ? isol_tck ? isol_ti ? isol_ex ? testen ? adv10/lan_disable# and supporting circuits ? actled#, spdled#, and liled# and supporting circuits table 3. usage modes 1, 2, 3, and 4 mode benefit mode 0: 82562et compatible. no bom changes necessary for equivalent performance to 82562et. mode 1: led configuration b and single- pin lan disable. usability and reduced bom cost. mode 2: same as mode 1, except led configuration c. usability and reduced bom cost. mode 3: led configuration b, single pin lan disable, and enhanced tx mode a usability, reduced bom cost, and stronger tx drive strength. refer to section 3.1.2 . mode 4: same as mode 3, except led configuration c. see table note a. usability, reduced bom cost, and stronger tx drive strength. refer to section 3.1.2 . a. only use this mode if advised to do so by an intel representative to compensate for board design issues affecting ieee compliance.
82562G ? networking silicon 8 datasheet 3.1.2 enhanced tx mode the enhanced tx mode speeds up the rise and fall tim es of the 100 mb signal. this was done so the 82562G can have improved ieee phy conformance requirements over a more capacitive analog front end (afe); usually caused by long traces or di fferential switches that customers use, usually on mobile platforms. however, running an 82562G device in enhanced mode increases the radiated emissions seen from the lan solu tion. the increase in radiated em issions may or may not impact the dut?s ability to pass regulatory requirements, as it will depend largely on the design of the afe. the enhanced mode should only be used wh en 100base-tx rise/fall times cannot be met in the normal 82562G mode. consult an intel representative if you are considering using this mode.
networking silicon ? 82562G datasheet 9 4.0 82562G signal descriptions 4.1 signal type definitions 4.2 twisted pair ethernet (tpe) pins 4.3 external bias pins type name description i input input pin to the 82562G. o output output pin from the 82562G. i/o input/output multiplexed input and output pin to and from the 82562G. mlt multi-level analog i/o multi-level analog pin used for input and output. b bias bias pin used for ground connection th rough a resistor or an external voltage reference. dps digital power supply digital power or ground pin for the 82562G. aps analog power supply analog power or ground pin for the 82562G. pin name pin number type description tdp tdn 10 11 mlt transmit differential pair. the transmit differential pair sends serial bit streams to the unshielded twisted pair (utp) cable. the differential pair is a two-level signal in 10base-t (manchester) mode and a three-level signal in 100base-tx mode (mlt-3). these signals directly interface with the isolation transformer. rdp rdn 15 16 mlt receive differential pair. the receive differential pair receive the serial bit stream from an unshielded twisted pair (utp) cable. the differential pair is a two-level signal in 10base-t mode (manchester) or a three-level signal in 100base-tx mode (mlt-3). these signals directly interface with an isolation transformer. pin name pin number type description rbias10 4 b reference bias resistor (100 mbps). this pin should be connected to a pull-down resistor. a a. based on some board designs, rbias100 and rbias10 values may need to be increased/decreased to compensate for high/ low mdi transmit amplitude. see the 82562G/gt and 82562et/em lan on motherboard design guide for more information. rbias100 5 b reference bias resistor (10 mbps). this pin should be connected to a pull-down resistor. a
82562G ? networking silicon 10 datasheet 4.4 clock pins 4.5 platform lan connect interface pins pin name pin number type description x1 46 i crystal input clock. x1 and x2 can be driven by an external 25 mhz crystal of 30 ppm or better. otherwise, x1 is driven by an external metal- oxide semiconductor (mos) level 25 mhz oscillator when x2 is left floating. x2 47 o crystal output clock. x1 and x2 can be driven by an external 25 mhz crystal of 30 ppm or better. pin name pin number type description jclk 39 o lan connect clock. the lan connect clock is driven by the 82562G on two frequencies depending on operation speed. when the 82562G is in 100base-tx mode, jclk drives a 50 mhz clock. otherwise, jclk drives a 5 mhz clock for 10base-t. the jclk does not stop during normal operation. jrstsync 42 i reset/synchronize. this is a multiplexed pin and is driven by the media access control (mac) layer device. its functions are: ? reset. when this pin is a sserted beyond one lan connect clock period, the 82562G uses this signal reset. to ensure reset of the 82562G, the reset signal should remain active for at least 500 s. ? synchronize. when this pin is activated synchronously, for only one lan connect clock period, it is used to synchronize the mac and phy on lan connect word boundaries. jtxd[2:0] 45, 44, 43 i lan connect transmit data. the lan connect transmit pins are used to transfer data from the mac device to the 82562G. these pins are used to move transmitted data and real time control and management data. they also transmit out of band control data from the mac to the phy. the pins should be fully synchronous to jclk. jrxd[2:0] 37, 35, 34 o lan connect receive data. the lan connect receiv e pins are used to transfer data from the 82562G to the mac device. these pins are used to move received data and real time control and management data. they also move out of band control data from the phy to the mac. these pins are synchronous to jclk.
networking silicon ? 82562G datasheet 11 4.6 led pins 4.7 miscellaneous control pins pin name type description liled# o link integrity led. the liled# signal has three logic modes. the led configurations are listed in table 2, ?led logic functionality? . actled# o activity led. the led is active low and the activity led signal indicates either receive or transmit activity. when no activity is present, the led is off. the activity led will flicker when activity is present. t he flicker rate depends on the activity load. if address matching mode is enabled by the mac, this pin will also indicate address match events on previously received frames. spdled# o speed led. the spdled# signal has three logic modes. the led configurations are listed in table 2, ?led logic functionality? . pin name type description adv10/ lan_disable# i advertise 10 mbps only. the advertise 10 mbps only signal is asserted high, and the 82562G advertises only 10base- t technology during auto-negotiation processes in this state. otherwise, the 82562G advertises all of its technologies. note: adv10 has an internal 10 k ? pull-down resistor. lan disable in 82562G mode. in the 82562G operating mode, this pin is used as a lan disable signal. when it is driv en low, the device is fully powered down. isol_tck i test clock. the test clock signal sets the device into asynchronous test mode in conjunction with the test input, test execute and test enable pins (refer to table 1, ?82562G hardware configuration? ). in the manufacturing test mode, it acts as the test clock. note: isol_tck has an internal 10 k ? pull-down resistor. isol_ti i test input. the test input signal sets the device into asynchronous test mode in conjunction with the test clock, test execute and test enable pins (refer to table 1, ?82562G hardware configuration? ). in the manufacturing test mode, it acts as the test data input pin. note: isol_ti has an internal 10 k ? pull-down resistor. isol_exec i test execute. the test execute signal sets the device into asynchronous test mode in conjunction with the test clock, test input, and test enable pins (refer to table 1, ?82562G hardware configuration? ). in the manufacturing test mode, it places the command that was entered through the ti pin in the instruction register. note: isol_exec has an internal 10 k ? pull-down resistor. tout o test output. the test output pin is used for boundary xor scan output. in the manufacturing test mode, it acts as the test output port. testen i test enable. the test enable pin is used to enable test mode and should be externally pulled up to v cc using a 200 ? resistor to allow xor tree test mode.
82562G ? networking silicon 12 datasheet 4.8 power and ground connections pin name pin number type description vcc vccp vcca vcca2 vcct 1, 25 36, 40 2, 7, 9, 12, 14, 17 dps digital 3.3 v power. these pins should be connected to the main digital power supply. vss vssp vssa vssa2 8, 13, 18 24, 48 33, 38 3 6 dps digital ground. these pins should be connected to the main digital ground. vccr 19, 23 aps analog power. vssr 20, 22 aps analog ground. these pins should not be isolated from the main digital.
networking silicon ? 82562G datasheet 13 5.0 physical layer interface functionality the 82562G supports a direct glueless interface to all components that comply with the lan connect specification. 5.1 100base-tx mode 5.1.1 100base-tx transmit blocks the transmit subsection of the 82562G accepts 3 bit wide data from the lan connect unit. another subsection passes data unconditionally to the 4b/5b encoder. the 4b/5b encoder accepts nibble-wide data (4 bi ts) from the csma unit and compiles it into 5- bit-wide parallel symbols. these symbols are scramb led and serialized into a 125 mbps bit stream, converted by the analog transmit driver into a mlt-3 waveform format, and transmitted onto the unshielded twisted pair (utp) or shielded twisted pair (stp) wire. 5.1.1.1 100base-tx 4b/5b encoder the 4b/5b encoder complies with the ieee 802.3u 100base-tx standard. four bits are encoded according to the transmit 4b/5b lookup table. the lookup table matches a 5-bit code to each 4-bit code. the table below illustrate s the 4b/5b encoding scheme associated with the given symbol. table 4. 4b/5b encoder symbol 5b symbol code 4b nibble code 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 a 10110 1010 b 10111 1011 c 11010 1100 d 11011 1101 e 11100 1110 f 11101 1111 i 11111 inter packet idle symbol (no 4b)
82562G ? networking silicon 14 datasheet 5.1.1.2 100base-tx scrambler and mlt-3 encoder data is scrambled in 100base-tx in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. the scrambler logic accepts 5 bits from the 4b/5b encoder block and presents the scrambled data to the mlt-3 encoder. the 82562G implements the 11-bit stream cipher scrambler as adopted by the ansi xt3t9.5 committee for utp operation. the cipher equation used is: x[n] = x[n-11] + x[n-9] (mod 2) the mlt-3 encoder receives the scrambled non-re turn to zero (nrz) data stream from the scrambler and encodes the stream into mlt-3 for presentation to the driver. mlt-3 is similar to nrz1 coding, but three levels are output instead of two. the three output levels are positive, negative and zero. when an nrz ?0? arrives at the input of the encoder, the last output level is maintained (either positive, negative or zero). when an nrz ?1? arrives at the input of the encoder, the output steps to the next level. the order of steps is negative-zero-positive-zero which continues periodically. refer to ieee 802.3 specification for details. 5.1.1.3 100base-tx transmit framing the 82562G does not differentiate between the fiel ds of the mac frame containing preamble, start of frame delimiter, data and cyclic redundancy check (crc). the 82562 encodes the first byte of the preamble as the ?jk? symbol, encodes all ot her pieces of data according to the 4b/5b lookup table, and adds the ?tr? code after the end of the packet. the 82562 scrambles and serializes the data into a 125 mbps stream, encodes it as mlt-3, and drives it onto the wire. j 11000 1st start of packet symbol 0101 k 10001 2nd start of packet symbol 0101 t 01101 1st end of packet symbol r 00111 2nd end of packet symbol and flow control v 00000 invalid v 00001 invalid v 00010 invalid v 00011 invalid h 00100 invalid v 00101 invalid v 00110 invalid v 01000 invalid v 01100 invalid v 10000 flow control s v 11001 invalid symbol 5b symbol code 4b nibble code
networking silicon ? 82562G datasheet 15 5.1.1.4 transmit driver the transmit differential lines ar e implemented with a digital slop e controlled current driver that meets twisted pair physical media device (tp- pmd) specifications. current is sunk from the isolation transformer by the transmit differential pins. the conceptual transmit differential waveform for 100 mbps is illustrated in the following figure. figure 3. conceptual transmit differential waveform the magnetics module external to the 82562G converts i tdp and i tdn to 2.0 v pp , as required by the tp-pmd specification. the sa me magnetics used for 100base-tx mode can also work in 10base-t mode. 5.1.2 100base-tx receive blocks the receive subsection of the 82562G accepts 100base-tx mlt-3 data on the receive differential pair. due to the advanced digital signal processing design techniques employed, the 82562G will accurately receive valid data from category 5 (cat5) utp and type 1 stp cable of length well in excess of 100 meters. 5.1.2.1 adaptive equalizer the distorted mlt-3 signal at the end of the wi re is restored by the equalizer. the equalizer performs adaptation based on the shape of the received signal, equalizing the signal to meet superior data dependent jitter performance. 5.1.2.2 receive clock and data recovery the clock recovery circuit uses advanced digita l signal processing technology to compensate for various signal jitter causes. the circuit recovers the 125 mhz clock and data and presents the data to the mlt-3 decoder. 5.1.2.3 mlt-3 decoder, descrambler, and receive digital section the 82562G first decodes the mlt-3 data, and then the descrambler reproduces the 5b symbols originated in the transmitter. the descrambling is based on synchronization to the transmission of the 11-bit linear feedback shift register (lfsr) during an idle phase. the data is decoded at the 4b/5b decoder. after the 4b symbols are obtained, the 82562G outputs the receive data to the csma unit.
82562G ? networking silicon 16 datasheet in 100base-tx mode, the 82562G can detect errors in receive data in a number of ways. any of the following conditions is considered an error: ? link integrity fails in the middle of frame reception. ? the start of stream delimiter ?jk? symbol is not fully detected after idle. ? an invalid symbol is detected at the 4b/5b decoder. ? idle is detected in the middle of a frame (before ?tr? is detected). 5.2 10base-t mode 5.2.1 10base-t transmit blocks 5.2.1.1 10base-t manchester encoder after the 2.5 mhz clocked data is serialized in a 10 mbps serial stream, the 20 mhz clock performs the manchester encoding. the manchester code always has a mid-bit transition. the boundary transition occurs only when the data is the same from bit to bit. for example, if the value is 11b, then the change is from low to high within the boundary. 5.2.1.2 10base-t driver and filter since 10base-t and 100base-tx have different filtration needs, both filters are implemented inside the chip. the 82562G supports both technologies through one pair of transmit differential pins and by externally sharing the same magnetics. in 10 mbps mode the line drivers use a pre-distortion algorithm to improve jitter tolerance. the line drivers reduce their drive level during the second half of ?wide? (100 ns) manchester pulses and maintain a full drive level during all narrow (50 ns) pulses and the first half of the wide pulses. this reduces line overcharging during wide pulses, a major source of jitter. 5.2.2 10base-t receive blocks 5.2.2.1 10base-t manchester decoder the 82562G performs manchester decoding and timing recovery in 10base-t mode. the manchester encoded data stream is decoded from the receive differential pair. this data is transferred to the controller at 2.5 mhz/nibble. the high-performance circuitry of the 82562G exceeds the ieee 802.3 jitter requirements. 5.2.2.2 10base-t twisted pair ethernet (tpe) receive buffer and filter in 10 mbps mode, data is expected to be recei ved on the receive differential pair after passing through isolation transformers. the filter is implemented inside the 82562G for supporting single magnetics that are shared with the 100base-tx si de. the input differential voltage range for the twisted pair ethernet (tpe) receiver is greater th an 585 mv and less than 3.1 v. the tpe receive buffer distinguishes valid receive data, link test pulses, and the idle cond ition, according to the requirements of the 10base-t standard. the following line activity is determined to be inactive and is rejected as invalid data:
networking silicon ? 82562G datasheet 17 ? differential pulses of peak magnitude less than 300 mv. ? continuous sinusoids with a differential amplitude less than 6.2 v pp and frequency less than 2 mhz. ? sine waves of a single cycle duration starting with 0 or 180 phase that have a differential amplitude less than 6.2 v pp and a frequency of at least 2 mhz and not more than 16 mhz. these single-cycle sine waves are discarded only if they are preceded by 4 bit times (400 ns) of silence. all other activity is determined to be either data, link test pulses, auto-negotiation fast link pulses, or the idle condition. 5.3 analog references the 82562G has two inputs, rbias100 and rbias10, that require external resistor connections to set biases for its internal analog section. the input pins are sensitive to the resistor value and experimentation is required to determine the correct values for any given layout. note that the values listed in figure 4 are starting values. also, resistors of 1% tolerance should be used. 5.4 dynamic reduced power & auto plugging detection the 82562G can be configured to support a dynamic reduced power mode. this mode reduces power consumption of the 82562G when lan activ ity is not present. the reduced power mode decreases power consumption from 300 mw to about 50 mw and is based on automatic detection of cable plugging. if the 82562G is configured to support dynamic power reduction, it enters the reduced power mode whenever a cable is not conn ected to the device. in reduced power mode, the 82562G shuts off the link circuits, except the circuit used for the automatic plugging detection. on the lan connect side, the entire interface rema ins active, including full access to all media independent interface (mii) registers. in this m ode, the 82562G switches to the 10 mbps speed interface (5 mhz for lan connect). thus, the redu ced power mode is fully transparent to driver. figure 4. analog references 82562 rbias100 rbias10 619 1% 549 1% 649 ? 1% 619 ? 1%
82562G ? networking silicon 18 datasheet 5.4.1 auto plugging detection the 82562G senses the link all the time. if it detects loss of any link activity for more than 6.6 seconds, it indicates to the media access controlle r (mac) an ?unplugged state? by resetting the sql lan connect control bit. if the 82562G is in reduced power mode and link activity is detected, the 82562G notifies the mac (in less than 1 second) that it is in a ?plugged state? by setting the sql lan connect control bit. link activity detection is based on energy detection. 5.4.2 dynamic reduced power the 82562G can be configured to support dynamic reduced power. in the dynamic reduced power mode, the 82562G transitions to reduced power mode when an unplugged state is detected. the 82562G will only return to full power if the reduced power bit on the lan connect is reset and a plugged state is detected. however, if the 82562G is not configured to support dynamic reduced power, the 82562G operates according to the lan connect power-down bit (in other words, the 82562G operates in reduced power mode only if the lan connect power-down bit is set). 5.4.3 configuration the dynamic reduced power mode is configured through bit 13 of register 16. the default value is disabled (0). the status of the 82562G can be read through bits 10:9 of register 16. when the 82562G is in reduced power mode, these two bits are set to 1b. the 82562G plc can enter a reduced power state manua lly through bit 11 of register 0. this bit is ored with the lan connect power down bit, wh ich allows the 82562G to enter a reduced power state. table 5. register 16 (10 hexadecimal): plc status, control and address data bit name description read/write 13 dynamic reduced power down 0 = automatic reduced power down enabled 1 = automatic reduced power down disabled (default) read/write 10 100base-tx power down the 100base-tx power down bit indicates the power state. 0 = normal operation (default) 1 = power down read only 9 10base-t power down the 10base-t power down bit indicates the power state. 0 = normal operation (default) 1 = power down read only table 6. register 0: control data bit name description read/write 11 reduced power down 0 = reduced power down disabled (normal operation; default) 1 = reduced power down enabled read/write
networking silicon ? 82562G datasheet 19 6.0 platform lan connect registers the following subsections describe phy regist ers that are accessible through the lan connect management frame protocol. acronyms mentioned in the registers are defined as follows: sc: self cleared. ro: read only. rw: read/write. e: eeprom setting affects content. ll: latch low. lh: latch high. 6.1 medium dependent interface (mdi) registers 0 through 7 6.1.1 register 0: control register bit definitions bit(s) name description default r/w 15 reset this bit sets the status and control register of the phy to their default states and is self-clearing. the phy returns a value of one until the reset process has completed and accepts a read or write transaction. 0 = normal operation 1 = phy reset 0rw sc 14 loopback this bit enables loopback of transmit data nibbles to the receive data path. the phy receive circuitry is isolated from the network. note that this may cause the descrambler to lose synchronization and produce 560 ns of ?dead time.? note also that the loopback configuration bit takes priority over the loopback mdi bit. 0 = loopback disabled (normal operation) 1 = 1 = loopback enabled 0rw 13 speed selection this bit is valid on read and controls speed when auto- negotiation is disabled. 0 = 10 mbps 1 = 100 mbps 1rw 12 auto-negotiation enable this bit enables auto-negotiation. bits 13 and 8, speed selection and duplex mode, respectively, are ignored when auto-negotiation is enabled. 0 = auto-negotiation disabled 1 = auto-negotiation enabled 1rw 11 reduced power down this bit sets the phy into a low power mode. 0 = power down disabled (normal operation) 1 = power down enabled 0rw
82562G ? networking silicon 20 datasheet 6.1.2 register 1: status register bit definitions 10 isolate this bit allows the phy to isolate the medium independent interface. the phy is disconnected from the lan connect block on both the transmit and receive side. 0 = normal operation 1 = isolates internal medium independent interface 0rw 9 restart auto- negotiation this bit restarts the auto-negotiation process and is self- clearing. 0 = normal operation 1 = restart auto-negotiation process 0rw sc 8 duplex mode this bit controls the duplex mode when auto-negotiation is disabled. when auto-negotiation is enabled this bit is read only and always equals 1b. when the phy is placed in loopback mode, the behavior of the phy shall not be affected by the status of this bit. 0 = half duplex 1 = full duplex 0rw/ ro 7 collision test this bit is not used in the 82562G and has a default value of 1b. (if it is used in other devices, it forces a collision in response to the assertion of the transmit enable signal.) 1rw 6:0 reserved these bits are reserved and should be set to 0b. 0 rw bit(s) name description default r/w 15 reserved this bit is reserved and should be set to 0b. 0 ro 14 100base-tx full-duplex this bit enables 100base- tx full-duplex operation and is dependent on adv10. if adv10 is active, the default value is 0. 0 = phy unable to perform full-duplex 100base-tx 1 = phy able to perform full-duplex 100base-tx 1ro 13 100 mbps half- duplex this bit enables 100base-tx half-duplex operation and is dependent on adv10. if adv10 is active, the default value is 0. 0 = phy unable to perform half-duplex 100base-tx 1 = phy able to perform half-duplex 100base-tx 1ro 12 10 mbps full- duplex this bit enables 10base-t full duplex operation. 0 = phy unable to perform full-duplex 10base-t 1 = phy able to perform full-duplex 10base-t 1ro 11 10 mbps half- duplex this bit enables 10base-t half-duplex operation. 0 = phy unable to perform half-duplex 10base-t 1 = phy able to perform half-duplex 10base-t 1ro 10:7 reserved these bits are reserved and should be set to 0b. 0 ro 6 management frames preamble suppression this bit allows the 82562G to receive management frames with suppr essed preamble. 0 = phy will not accept management frames with preamble suppressed 1 = phy will accept management frames with preamble suppressed 0ro bit(s) name description default r/w
networking silicon ? 82562G datasheet 21 6.1.3 register 2: phy identifier register bit definitions 6.1.4 register 3: phy identifier register bit definitions 6.1.5 register 4: auto-negotiation adve rtisement register bit definitions 5 auto-negotiation complete this bit reflects status of the auto-negotiation process. 0 = auto-negotiation process has not completed 1 = auto-negotiation process completed 0ro 4 remote fault 0 = no remote fault condition detected 1 = remote fault condition detected 0ro 3 auto-negotiation ability this bit reflects the phy?s auto-negotiation ability status. 0 = phy is unable to perform auto-negotiation 1 = phy is able to perform auto-negotiation 1ro 2 link status this bit reflects link status. 0 = invalid link detected 1 = valid link established 0ro ll 1 jabber detect this bit is used only in 10base-t mode. 0 = no jabber condition detected 1 = jabber condition detected 0ro lh 0 extended capability this bit enables the extended register capabilities. 0 = extended register capabilities disabled 1 = extended register capabilities enabled 1ro bit(s) name description default r/w 15:0 phy id (high byte) value: 02a8 hexadecimal -- ro bit(s) name description default r/w 15:0 phy id (low byte) value: 0330 hexadecimal for 82562G plc (and 82562Gz) -- ro 15:0 phy id (low byte) value: 0310 hexadecimal for 82562G -- ro bit(s) name description default r/w 15 next page this bit is a constant 0, transmit primary capability data page. 0ro 14 reserved this bit is reserved and should be set to 0b. 0 ro bit(s) name description default r/w
82562G ? networking silicon 22 datasheet 6.1.6 register 5: auto-negotiation link partner ability register bit definitions 6.1.7 register 6: auto-negotiation ex pansion register bit definitions 13 remote fault 0 = no remote fault 1 = indicate link partner?s remote fault 0rw 12:5 technology ability field technology ability field is an 8-bit field containing information indicating supported technologies specific to the selector field value. 0010 1111 rw 4:0 selector field the selector field is a 5-bit field identifying the type of message to be sent by auto-negotiation. this field is read only and contains a value of 00001b, ieee standard 802.3. 00001 ro bit(s) name description default r/w 15 next page this bit reflects the phy?s link partner?s next page ability. -- ro 14 acknowledge this bit is used to indicate that the 82562G has successfully received its link partner?s auto- negotiation advertising ability. -- ro 13 remote fault this bit reflects the phy?s link partner?s remote fault condition. -- ro 12:5 technology ability field this bit reflects the phy?s link partner?s technology ability field. -- ro 4:0 selector field this bit reflects the phy?s link partner?s selector field. -- ro bit(s) name description default r/w 15:5 reserved these bits are reserved and should be set to 0. 0 ro 4 parallel detection fault this bit clears itself on read. 0 = no fault detected via parallel detection 1 = fault detected via parallel detection (multiple link fault occurred) 0ro sc lh 3 link partner next page able 0 = link partner is not next page able 1 = link partner is next page able 0ro 2 next page able 0 = 0 = local drive is not next page able 1 = local drive is next page able 0ro 1 page received this bit clears itself on read. 0 = new page not received 1 = new page received 0ro sc lh 0 link partner auto- negotiation able 0 = link partner is not auto-negotiation able 1 = link partner is auto-negotiation able 0ro bit(s) name description default r/w
networking silicon ? 82562G datasheet 23 6.2 mdi registers 8 through 15 registers 8 through 15 are reserved for ieee. 6.3 mdi registers 16 through 31 6.3.1 register 16: phy status and control register bit definitions bit(s) name description default r/w 15:14 reserved these bits are reserved and should be set to 00b. 00 rw 13 reduced power down disable this bit disables the automatic reduced power down. 0 = enable automatic reduced power down 1 = disable automatic reduced power down 1rw 12 reserved this bit is reserved and should be set to 0b. 0 rw 11 receive de- serializer in-sync indication this bit indicates status of the 100base-tx receive de-serializer in-sync. -- ro 10 100base-tx power-down this bit indicates the power state of 100base-tx phy unit. 0 = normal operation 1 = power-down 1ro 9 10base-t power-down this bit indicates the power state of 10base-t phy unit. 0 = normal operation 1 = power-down 1ro 8 polarity this bit indicates 10base-t polarity. 0 = normal polarity 1 = reverse polarity -- ro 7 reserved this bit is reserved and should be set to 0b. 0 ro 6:2 phy address these bits contain the sampled phy address. -- ro 1 speed this bit indicates the auto-negotiation result. 0 = 10 mbps 1 = 100 mbps -- ro 0 duplex mode this bit indicates the auto-negotiation result. 0 = half-duplex 1 = full-duplex -- ro
82562G ? networking silicon 24 datasheet 6.3.2 register 17: phy unit special control bit definitions 6.3.3 register 18: reserved bit(s) name description default r/w 15 scrambler by- pass 0 = normal operations 1 = by-pass scrambler 0rw 14 by-pass 4b/5b 0 = normal operation 1 = 4 bit to 5 bit by-pass 0rw 13 force transmit h- pattern 0 = normal operation 1 = force transmit h-pattern 0rw 12 force 34 transmit pattern 0 = normal operation 1 = force 34 transmit pattern 0rw 11 valid link 0 = normal operation 1 = 100base-tx valid link 0rw 10 symbol error enable 0 = normal operation 1 = symbol error output is enabled 0rw 9 carrier sense disable this bit controls the receive 100 carrier sense disable function. 0 = carrier sense enabled 1 = carrier sense disabled 0rw 8 disable dynamic power-down 0 = dynamic power-down enabled 1 = dynamic power-down disabled 0rw 7 auto-negotiation loopback 0 = auto-negotiation normal mode 1 = auto-negotiation loopback 0rw 6mdi tri-state 0 = normal operation 1 = mdi tri-state (transmit driver tri-states) 0rw 5 force polarity 0 = normal polarity 1 = reversed polarity 0rw 4auto polarity disable 0 = normal polarity operation 1 = auto polarity disabled 0rw 3 squelch disable 0 = normal squelch operation 1 = 10base-t squelch test disable 0rw 2 extended squelch 1 = 10base-t extended squelch control enabled 0 = 10base-t extended squelch control disabled 0rw 1 link integrity disable 0 = normal link integrity operation 1 = link disabled 0rw 0 jabber function disable 0 = normal jabber operation 1 = jabber disabled 0rw bit(s) name description default r/w 15:0 reserved these bits are reserved and should be set to a constant 0. 0ro
networking silicon ? 82562G datasheet 25 6.3.4 register 19: 100base-tx receive false carrier counter bit definitions 6.3.5 register 20: 100base-tx receiv e disconnect counter bit definitions 6.3.6 register 21: 100base-tx receive error frame counter bit definitions 6.3.7 register 22: receive symbol error counter bit definitions 6.3.8 register 23: 100base-tx receive premature end of frame error counter bit definitions bit(s) name description default r/w 15:0 receive false carrier these bits are used for the false carrier counter. -- ro sc bit(s) name description default r/w 15:0 disconnect event this field contains a 16-bit counter that increments for each disconnect event. the counter stops when it is full and self-clears on read -- ro sc bit(s) name description default r/w 15:0 receive error frame this field contains a 16-bi t counter that increments once per frame for any receive error condition (such as a symbol error or premature end of frame) in that frame. the counter stops when it is full and self-clears on read. -- ro sc bit(s) name description default r/w 15:0 symbol error counter this field contains a 16-bit counter that increments for each symbol error. the counter stops when it is full and self-clears on read. in a frame with a bad symbol, each sequential six bad symbols count as one. -- ro sc bit(s) name description default r/w 15:0 premature end of frame this field contains a 16-bit counter that increments for each premature end of frame event. the counter stops when it is full and self-clears on read. -- ro sc
82562G ? networking silicon 26 datasheet 6.3.9 register 24: 10base-t receive end of frame error counter bit definitions 6.3.10 register 25: 10base-t transmit jabber detect counter bit definitions bit(s) name description default r/w 15:0 end of frame counter this is a 16-bit counter that increments for each end of frame event. the counter stops when it is full and self-clears on read. -- ro sc bit(s) name description default r/w 15:0 jabber detect counter this is a 16-bit counter that increments for each jabber detection event. the counter stops when it is full and self-clears on read. -- ro sc
networking silicon ? 82562G datasheet 27 6.3.11 register 27: phy unit special control bit definitions bit(s) name description default r/w 15:6 reserved these bits are reserved and should be set to a constant 0. 0ro 5 switch probe mapping this bit switches the mapping on the leds. the led mapping is described below in bits 2:0, led switch control. this bit should always be set to 0b. 0rw 4 new mode if this bit equals 0, the device is in 82562ez (or 82562et) mode. if this bit equals 1, the device is in 82562G mode. ro 3 100base-tx receive jabber disable this bit enables the carrier sense disconnection while the phy is in jabber mode at 100 mbps speed. 0rw 2:0 led switch control value 000 001 010 011 100 101 110 111 actled# activity speed speed activity off off on on liled# link collision link collision off on off on 000 rw
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networking silicon ? 82562G datasheet 29 7.0 82562G test port functionality the 82562G?s xor tree test access port (tap) is the access point for test data to and from the device. the port provides the ability to perform basic production level testing. 7.1 asynchronous test mode an asynchronous test mode is supported for system level design use. the modes are selected through the use of the test port input pins (testen, isol_tck, isol_ti and isol_exec) in static combinations. during normal operation the test pins must be pulled down through a resistor (pulling test high enables the test mode). all other port inputs may have a pull-down at the designers discretion. 7.2 test function description the 82562G tap mode supports several tests that can be used in board level design. these tests can help verify basic functionality and test the integrity of solder connections on the board. the tests are described in the following sections. the xor tree test mode is the most useful of the asynchronous test modes. it enables the placement of the 82562G to be validated at board test. the xor tree was chosen for its speed advantages. modern automated test equipment (a te) can perform a complete peripheral scan without support at the board level. this command co nnects all output signals of the input buffers in the device periphery into an xor tree scheme. all output drivers of the output-buffers, except the test output (tout) pin, are put into high-z mode. th ese pins are driven to affect the tree?s output. any hard strapped pins will prevent the tester from scanning correctly. the xor tree test mode is obtained by placing the test pins in the following configuration (refer to table 7 ): testen = 1 isol_tck = 0 isol_ti = 0 isol_exec = 0. table 7. xor tree chain order chain order chain 1jtxd2 2jtxd1 3jtxd0 4jrstsync 5 adv10 (lan_disable#) 6jclk 7jrxd2 8jrxd1 9jrxd0 10 actled#
82562G ? networking silicon 30 datasheet the following pins are not included in the xor tree chain: x1, isol_tck, isol_exec, isol_ti and testen. 11 spdled# 12 liled# xor tree output tout table 7. xor tree chain order chain order chain
networking silicon ? 82562G datasheet 31 8.0 electrical and timing specifications 8.1 absolute maximum ratings maximum ratings are listed below: case temperature under stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to 135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 c to 150 c supply voltage with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to 3.45 v output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 v to 3.45 v input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v cc to 3.45 v stresses above the listed absolute maximum ratings may cause permanent damage to the 82562G device. this is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8.2 dc characteristics 8.2.1 x1 clock dc specifications notes: 1. this characteristic is only characterized, not tested. it is valid for digital pins only. table 8. general dc specifications symbol parameter condition min typical max units notes v cc supply voltage 3.0 3.3 3.45 v t temperature minimum/maximum case temperature 085c p power consumption 10/100mbps (transmitter on) 300 mw reduced power 50 mw auto-negotiation 200 mw table 9. x1 clock dc specifications symbol parameter condition min typical max units notes v il input low voltage 0.8 v v ih input high voltage 2.0 v i ilih input leakage currents 0 < v in < v cc 10 a c i input capacitance 8pf 1
82562G ? networking silicon 32 datasheet 8.2.2 lan connect interface dc specifications notes: 1. this characteristic is only characterized, not tested. it is valid for digital pins only. 8.2.3 led dc specifications 8.2.4 10base-t voltage and current dc specifications notes: current is measured between the transmit diff erential pins (tdp and tdn) at 3.3 v. 1. r l is the resistive load measured across the transmit differential pins, tdp and tdn. table 10. lan connect interface dc specifications symbol parameter condition min typical max units notes v ccj input/output supply voltage 3.0 3.45 v v il input low voltage -0.5 0.3v ccj v v ih input high voltage 0.6v ccj v ccj + 0.5 v i il input leakage current 0 < v in < v ccj 10 a v ol output low voltage i out = 1500 a 0.1v ccj v v oh output high voltage i out = -500 a 0.9v ccj v c in input pin capacitance 8pf 1 table 11. led dc specifications symbol parameter condition min typical max units notes v olled output low voltage i out = 10 ma 0.7 v v ohled output high voltage i out = -10 ma 2.4 v table 12. 10base-t transmitter symbol parameter condition min typical max units notes v od10 output differential peak voltage r l = 100 ? 2.2 2.8 v 1
networking silicon ? 82562G datasheet 33 notes: 1. the input differential resistance is measured across the receive differential pins, rdp and rdn. 8.2.5 100base-tx voltage and current dc specifications notes: current is measured between the transmit differential pins (tdp and tdn) at 3.3 v. 1. r l is the resistive load measured across the transmit differential pins, tdp and tdn. notes: 1. the input differential resistance is measured across the receive differential pins, rdp and rdn. table 13. 10base-t receiver symbol parameter condition min typical max units notes r id10 input differential resistance dc 10 k ? 1 v ida10 input differential accept peak voltage 5 mhz f 10 mhz 585 3100 mv v idr10 input differential reject peak voltage 5 mhz f 10 mhz 300 mv v icm10 input common mode voltage v cc/2 v table 14. 100base-tx transmitter symbol parameter condition min typical max units notes v od100 output differential peak voltage r l = 100 ? 0.95 1.0 1.05 v 1 table 15. 100base-tx receiver symbol parameter condition min typical max units notes r id100 input differential resistance dc 10 k ? 1 v ida100 input differential accept peak voltage 500 1200 mv v idr100 input differential reject peak voltage 100 mv v icm100 input common mode voltage v cc/2 v
82562G ? networking silicon 34 datasheet 8.3 ac characteristics figure 5 defines the conditions for timing measurements. the design must guarantee proper operation for voltage swings and slew rates that exceed the specified test conditions. 8.3.1 10base-t normal link pulse (nlp) timing parameters figure 5. ac test level conditions table 16. normal link pulse timing parameters symbol parameter condition min typical max units notes t6 t nlp_wid nlp width 10 mbps 100 ns t7 t nlp_per nlp period 10 mbps 8 16 24 ms input levels 1.4 v output levels v oh = 2.0 v v ol = 0.8 v figure 6. normal link pulse timings normal link pulse t7 t6
networking silicon ? 82562G datasheet 35 8.3.2 auto-negotiation fast link pulse (flp) timing parameters table 17. fast link pulse timing parameters symbol parameter condition min typical max units notes t8 t f lp_wid flp width (clock and data) 100 ns t9 t flp_clk_clk clock pulse to clock pulse period 111 125 139 s t10 t flp_clk_data clock pulse to data pulse period 55.5 62.5 69.5 s t11 t flp_bur_num pulses in one burst 17 33 # t12 t flp_bur_wid burst width 2 ms t13 t flp_bur_per flp burst period 8 16 24 ms figure 7. fast link pulse timings fast link pulse t10 t8 t9 clock pulse data pulse clock pulse flp bursts t12 t13
82562G ? networking silicon 36 datasheet 8.3.3 100base-tx transmitter ac specifications 8.3.4 reset (rstsync) ac specifications table 18. 100base-tx transmitter timing parameters symbol parameter condition min typical max units notes t14 t jit tdp/tdn differential output peak jitter hls data 1400 ps table 19. reset timing parameters symbol parameter condition min typical max units notes t58 t rst_wid reset pulse width 500 s t59 t pop_rst power-up to falling edge of reset 1000 s figure 8. reset timing parameters power up (vcc) reset t59 t58
networking silicon ? 82562G datasheet 37 9.0 package and pinout information 9.1 package information the 82562G is a lead-free 48-pin shrink small outline package (ssop) that supports leaded and lead-free designs. the package dimensions are shown in figure 9 . more information on intel device packaging is available in the intel packag ing handbook, which is available from the intel literature center or your local sales office. figure 9. dimension diagram for the 82562G plc 48-pin ssop
82562G ? networking silicon 38 datasheet 9.2 pinout information 9.2.1 82562G pin assignments table 20. 82562G pin assignments pin number pin name pin number pin name pin number pin name pin number pin name 1 vcc 13 vss 25 vcc 37 jrxd2 2 vcca 14 vcct 26 tout 38 vssp 3 vssa 15 rdp 27 liled# 39 jclk 4 rbias10 16 rdn 28 isol_ti 40 vccp 5 rbias100 17 vcct 29 isol_exec 41 adv10/lan_ disable# 6 vssa2 18 vss 30 isol_tck 42 jrstsync 7 vcca2 19 vccr 31 spdled# 43 jtxd0 8 vss 20 vssr 32 actled# 44 jtxd1 9 vcct 21 testen 33 vssp 45 jtxd2 10 tdp 22 vssr 34 jrxd0 46 x1 11 tdn 23 vccr 35 jrxd1 47 x2 12 vcct 24 vss 36 vccp 48 vss
networking silicon ? 82562G datasheet 39 9.2.2 82562G shrink small outline package diagram figure 10. 82562G pin out diagram 82562G pin diagram ssop48 rev 1.0 top view 1 2 6 5 4 3 7 8 9 10 11 12 13 14 15 16 17 32 33 37 36 35 34 38 39 40 41 42 43 44 45 46 47 48 vssr (aps) vccr (aps) vcct (aps) vss (dps) vss (dps) vssa (aps) rbias10 (b) rbias100 (b) vssa2 (aps) vcca2 (aps) tdp (mlt) vcca (aps) jtxd2 (i) jrxd2 (o) jrstsync vssp (dps) x1(i) x2 (o) vss (dps) adv10/ lan_disable# (i) isol_ti (i) 18 19 20 21 22 23 24 31 30 29 28 27 26 25 liled# (o) actled# (o) spdled# (o) tdn (mlt) vcct (aps) rdp (mlt) rdn (mlt) vcct (aps) vccr (aps) vssr (aps) vcct (aps) vss (dps) vss (dps) vcc (dps) jtxd1 (i) jtxd0 (i) jrxd1 (o) jrxd0 (o) vccp (dps) jclk (o) vccp (dps) vssp (dps) vcc (dps) s s s s o o isol_exec (i) tout (o) isol_tck (i) testen (i)
82562G ? networking silicon 40 datasheet note: this page is intentionally left blank.

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